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https://github.com/openhwgroup/cvw
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108 lines
4.4 KiB
Systemverilog
108 lines
4.4 KiB
Systemverilog
///////////////////////////////////////////
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// lsuArb.sv
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//
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// Written: Ross THompson and Kip Macsai-Goren
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// Modified: kmacsaigoren@hmc.edu June 23, 2021
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//
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// Purpose: LSU arbiter between the CPU's demand request for data memory and
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// the page table walker
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module lsuArb
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(input logic clk, reset,
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// from page table walker
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input logic SelPTW,
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input logic HPTWRead,
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input logic [`XLEN-1:0] HPTWPAdrE,
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output logic HPTWStall,
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// from CPU
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [1:0] AtomicM,
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input logic [`XLEN-1:0] MemAdrM,
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input logic [`XLEN-1:0] MemAdrE,
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input logic StallW,
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input logic PendingInterruptM,
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// to CPU
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output logic [`XLEN-1:0] ReadDataW,
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output logic DataMisalignedM,
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output logic CommittedM,
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output logic LSUStall,
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// to D Cache
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output logic DisableTranslation,
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output logic [1:0] MemRWMtoLRSC,
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output logic [2:0] Funct3MtoDCache,
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output logic [1:0] AtomicMtoDCache,
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output logic [`XLEN-1:0] MemAdrMtoDCache,
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output logic [`XLEN-1:0] MemAdrEtoDCache,
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output logic StallWtoDCache,
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output logic PendingInterruptMtoDCache,
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// from D Cache
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input logic CommittedMfromDCache,
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input logic DataMisalignedMfromDCache,
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input logic [`XLEN-1:0] ReadDataWfromDCache,
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input logic DCacheStall
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);
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logic [2:0] PTWSize;
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logic [`XLEN-1:0] HPTWPAdrM;
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// multiplex the outputs to LSU
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assign DisableTranslation = SelPTW; // change names between SelPTW would be confusing in DTLB.
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assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
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generate
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assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
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endgenerate
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mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM); // delay HPTWPAdr by a cycle
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assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
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assign MemAdrMtoDCache = SelPTW ? HPTWPAdrM : MemAdrM; // *** DH: I don't understand this logic 7/18/21. Why should PCF ever go here?
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assign MemAdrEtoDCache = SelPTW ? HPTWPAdrE : MemAdrE;
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assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
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// always block interrupts when using the hardware page table walker.
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assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
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// demux the inputs from LSU to walker or cpu's data port.
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// works without the demux 7/18/21 dh. Suggest deleting these and removing fromDCache suffix
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assign ReadDataW = /*SelPTW ? `XLEN'b0 : */ReadDataWfromDCache; // probably can avoid this demux
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assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
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// *** need to rename DcacheStall and Datastall.
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// not clear at all. I think it should be LSUStall from the LSU,
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// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
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//assign HPTWStall = SelPTW ? DCacheStall : 1'b1;
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assign HPTWStall = DCacheStall;
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assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
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assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
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endmodule
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