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263 lines
9.7 KiB
Systemverilog
263 lines
9.7 KiB
Systemverilog
///////////////////////////////////////////
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// bpred.sv
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 12, 2021
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// Modified:
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//
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// Purpose: Branch prediction unit
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// Produces a branch prediction based on branch history.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module bpred
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(input logic clk, reset,
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input logic StallF, StallD, StallE,
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input logic FlushF, FlushD, FlushE,
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// Fetch stage
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// the prediction
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input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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output logic [`XLEN-1:0] BPPredPCF,
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output logic SelBPPredF,
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// Update Predictor
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input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction
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// 1 hot encoding
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// return, jump register, jump, branch
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// *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class.
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// *** the specifics of how this is encode is subject to change.
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input logic PCSrcE, // AKA Branch Taken
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// Signals required to check the branch prediction accuracy.
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input logic [`XLEN-1:0] IEUAdrE, // The branch destination if the branch is taken.
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input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
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input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
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input logic [4:0] InstrClassE,
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// Report branch prediction status
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output logic BPPredWrongE,
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output logic BPPredDirWrongE,
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output logic BTBPredPCWrongE,
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output logic RASPredPCWrongE,
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output logic BPPredClassNonCFIWrongE
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);
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logic BTBValidF;
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logic [1:0] BPPredF, BPPredD, BPPredE, UpdateBPPredE;
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logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE;
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logic [`XLEN-1:0] BTBPredPCF, RASPCF;
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logic TargetWrongE;
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logic FallThroughWrongE;
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logic PredictionPCWrongE;
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logic PredictionInstrClassWrongE;
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// Part 1 branch direction prediction
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if (`BPTYPE == "BPTWOBIT") begin:Predictor
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twoBitPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.StallF(StallF),
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0] & ~StallE),
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.UpdatePrediction(UpdateBPPredE));
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end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
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globalHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.PCNextF(PCNextF),
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.BPPredF(BPPredF),
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// update
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.InstrClassE(InstrClassE),
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.BPInstrClassE(BPInstrClassE),
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.BPPredDirWrongE(BPPredDirWrongE),
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.PCE(PCE),
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.PCSrcE(PCSrcE),
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.UpdateBPPredE(UpdateBPPredE));
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end else if (`BPTYPE == "BPGSHARE") begin:Predictor
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gsharePredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.PCNextF(PCNextF),
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.BPPredF(BPPredF),
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// update
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.InstrClassE(InstrClassE),
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.BPInstrClassE(BPInstrClassE),
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.BPPredDirWrongE(BPPredDirWrongE),
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.PCE(PCE),
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.PCSrcE(PCSrcE),
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.UpdateBPPredE(UpdateBPPredE));
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end
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else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
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localHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0] & ~StallE),
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.PCSrcE(PCSrcE),
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.UpdatePrediction(UpdateBPPredE));
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end
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else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
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localHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0] & ~StallE),
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.PCSrcE(PCSrcE),
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.UpdatePrediction(UpdateBPPredE));
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end
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// this predictor will have two pieces of data,
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// 1) A direction (1 = Taken, 0 = Not Taken)
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// 2) Any information which is necessary for the predictor to built it's next state.
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// For a 2 bit table this is the prediction count.
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assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) |
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BPInstrClassF[3] |
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(BPInstrClassF[2] & BTBValidF) |
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BPInstrClassF[1] & BTBValidF) ;
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// Part 2 Branch target address prediction
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// *** For now the BTB will house the direct and indirect targets
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// *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
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BTBPredictor TargetPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.LookUpPC(PCNextF),
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.TargetPC(BTBPredPCF),
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.InstrClass(BPInstrClassF),
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.Valid(BTBValidF),
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// update
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.UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
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.UpdatePC(PCE),
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.UpdateTarget(IEUAdrE),
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.UpdateInvalid(PredictionInstrClassWrongE),
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.UpdateInstrClass(InstrClassE));
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// Part 3 RAS
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// *** need to add the logic to restore RAS on flushes. We will use incr for this.
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RASPredictor RASPredictor(.clk(clk),
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.reset(reset),
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.pop(BPInstrClassF[3] & ~StallF),
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.popPC(RASPCF),
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.push(InstrClassE[4] & ~StallE),
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.incr(1'b0),
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.pushPC(PCLinkE));
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assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF;
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// The prediction and its results need to be passed through the pipeline
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// *** for other predictors will will be different.
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flopenr #(2) BPPredRegD(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.d(BPPredF),
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.q(BPPredD));
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flopenr #(2) BPPredRegE(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.d(BPPredD),
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.q(BPPredE));
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// pipeline the class
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flopenrc #(5) InstrClassRegD(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(FlushD),
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.d(BPInstrClassF),
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.q(BPInstrClassD));
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flopenrc #(5) InstrClassRegE(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.clear(FlushE),
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.d(BPInstrClassD),
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.q(BPInstrClassE));
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// Check the prediction makes execution.
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// first check if the target or fallthrough address matches what was predicted.
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assign TargetWrongE = IEUAdrE != PCD;
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assign FallThroughWrongE = PCLinkE != PCD;
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// If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected
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// Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi
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// it must have selected the fall through.
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assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
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// The branch direction also need to checked.
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// However if the direction is wrong then the pc will be wrong. This is only relavent to checking the
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// accuracy of the direciton prediction.
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assign BPPredDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
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// Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated.
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// Also we want to track this in a performance counter.
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assign PredictionInstrClassWrongE = InstrClassE != BPInstrClassE;
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// We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about
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// the direction or class, but correct about the target we don't have the flush the pipeline. However we still
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// need this information to verify the accuracy of the predictors.
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//assign BPPredWrongE = ((PredictionPCWrongE | BPPredDirWrongE) & (|InstrClassE)) | PredictionInstrClassWrongE;
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assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
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// If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
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assign BTBPredPCWrongE = (InstrClassE[4] | InstrClassE[2] | InstrClassE[1]) & PredictionPCWrongE;
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// similar with RAS
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assign RASPredPCWrongE = InstrClassE[3] & PredictionPCWrongE;
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// Finally if the real instruction class is non CFI but the predictor said it was we need to count.
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assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
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// Update predictors
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satCounter2 BPDirUpdate(.BrDir(PCSrcE),
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.OldState(BPPredE),
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.NewState(UpdateBPPredE));
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endmodule
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