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https://github.com/openhwgroup/cvw
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52 lines
1.9 KiB
Systemverilog
52 lines
1.9 KiB
Systemverilog
///////////////////////////////////////////
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// rom_ahb.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip ROM, external to core
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rom_ahb import cvw::*; #(parameter cvw_t P,
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parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
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input logic HCLK, HRESETn,
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input logic HSELRom,
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input logic [P.PA_BITS-1:0] HADDR,
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input logic HREADY,
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input logic [1:0] HTRANS,
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output logic [P.XLEN-1:0] HREADRom,
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output logic HRESPRom, HREADYRom
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);
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localparam ADDR_WIDTH = $clog2(RANGE/8);
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localparam OFFSET = $clog2(P.XLEN/8);
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// Never stalls
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assign HREADYRom = 1'b1;
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assign HRESPRom = 1'b0; // OK
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// single-ported ROM
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rom1p1r #(ADDR_WIDTH, P.XLEN, PRELOAD)
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memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
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endmodule
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