Ross Thompson c9bdaceddb Fixed icache for 32 bit. ... Merge branch 'cache' into main		2021-04-22 16:45:29 -05:00
..
bpred.sv	Cherry Pick merge of Shreya's localhistory predictor changes into main.	2021-04-15 09:04:36 -05:00
BTBPredictor.sv	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
decompress.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
globalHistoryPredictor.sv	added localHistoryPredictor	2021-04-15 08:58:22 -05:00
gshare.sv	Switched to gshare from global history.	2021-03-18 16:05:59 -05:00
icache.sv	Fixed icache for 32 bit.	2021-04-22 16:45:29 -05:00
ifu.sv	Fixed icache for 32 bit.	2021-04-22 16:45:29 -05:00
localHistoryPredictor.sv	Cherry Pick merge of Shreya's localhistory predictor changes into main.	2021-04-15 09:04:36 -05:00
RAsPredictor.sv	RAS needs to be reset or preloaded. For now I just reset it.	2021-02-19 20:09:07 -06:00
satCounter2.sv	We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.	2021-02-15 14:51:39 -06:00
SramModel.sv	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.	2021-02-18 21:32:15 -06:00
twoBitPredictor.sv	Fixed forwarding around the 2 bit predictor.	2021-03-04 13:01:41 -06:00