mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
9e93f21990
Modified makefile riscv-dv to not simulation only generate tests. |
||
---|---|---|
.. | ||
imperas | ||
privileged | ||
covergen_footer.S | ||
covergen_header.S | ||
covergen.py | ||
Makefile | ||
PIPELINE.py | ||
testgen_footer.S | ||
testgen_header.S | ||
testgen.py |