Ross Thompson d6fa8d51d7 Modified sram1p1rw to support 3 different implementation styles. ... SRAM, Read first, and Write first.		2022-09-21 11:26:00 -05:00
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cache	Modified sram1p1rw to support 3 different implementation styles.	2022-09-21 11:26:00 -05:00
ebu	Fixed up IFU ahb interface names and widths.	2022-09-19 10:54:22 -05:00
fpu	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
generic	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
hazard	Added comments about planned changes.	2022-08-29 09:48:00 -05:00
ieu	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
ifu	Merge branch 'tempMain' into main	2022-09-20 13:57:38 -05:00
lsu	Merge branch 'tempMain' into main	2022-09-20 13:57:38 -05:00
mmu	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
muldiv	Clean up unused signals	2022-05-12 14:49:58 +00:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Cleaned up fcvt selection control to IEU and FPUIllegalInst signals	2022-08-23 12:17:19 -07:00
uncore	Added chip enables to sram.	2022-09-20 10:49:14 -05:00
wally	Found the ahb burst bug.	2022-09-17 20:30:01 -05:00
sdc