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bp-results
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Completed branch predictor benchmarking.
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2023-09-27 13:56:51 -05:00 |
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slack-notifier
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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wave-dos
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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bpred-sim.py
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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buildrootBugFinder.py
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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coverage
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tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
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2023-09-02 12:56:36 -07:00 |
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coverage-exclusions-rv64gc.do
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Exclusions for decoders with new parameterization
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2023-05-30 01:04:39 -07:00 |
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FPbuild.txt
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Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file
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2023-06-20 17:26:54 -05:00 |
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fpga-wave.do
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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GetLineNum.do
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track GetLinenum.do (tcl procedure to find line numbers to exclude)
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2023-04-12 15:58:38 -07:00 |
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imperas.ic
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Imperas commenting
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2023-11-10 08:26:32 -08:00 |
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lint-wally
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Config file cleanup
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2023-10-18 05:38:36 -07:00 |
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linux-wave.do
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Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data.
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2023-04-26 17:29:57 -05:00 |
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make-tests.sh
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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Makefile
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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makefile-memfile
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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regression-wally
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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run-imperas-linux.sh
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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run-imperasdv-tests.bash
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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rv64gc_CacheSim.py
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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sim-buildroot
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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sim-buildroot-batch
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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sim-imperas
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Revert "Update for new layout of ImperasDV files"
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2023-06-13 04:17:56 -07:00 |
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sim-testfloat
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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sim-testfloat-batch
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For some reason this was modified - I probably made a mistake - put back vsim
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2023-06-22 15:26:22 -05:00 |
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sim-wally
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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sim-wally-batch
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code review harris
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2023-10-31 12:27:41 -07:00 |
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test
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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testfloat.do
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Remove path for cvw.sv so its found
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2023-06-22 15:25:56 -05:00 |
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verilate
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Verilator improvements
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2023-11-04 03:21:07 -07:00 |
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wally-batch.do
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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wally-imperas-cov.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally-imperas-no-idv.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally-imperas.do
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Added missing files.
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2023-10-13 15:10:58 -05:00 |
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wally-linux-imperas.do
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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wally.do
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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wally.xrun
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Got xcelium running wally, but it fails to actually preload the memories.
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2023-07-12 13:56:57 -05:00 |
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wave-all.do
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Renamed regression to sim
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2023-02-02 14:48:23 -08:00 |
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wave-fpu.do
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Add reset to wave window
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2023-06-29 08:47:16 -05:00 |
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wave.do
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
