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			83 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
			
		
		
	
	
			83 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
#!/usr/bin/python3
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###########################################
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## probe.sh
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##
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## Written: Jacob Pease jacobpease@protonmail.com
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## Created: 16 August 2023
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## Modified: 16 August 2023
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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## https://github.com/openhwgroup/cvw
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
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## may obtain a copy of the License at
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##
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## https:##solderpad.org#licenses#SHL-2.1#
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the 
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
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## either express or implied. See the License for the specific language governing permissions 
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## and limitations under the License.
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################################################################################################
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import sys
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def usage():
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    print("Usage: ./probes name width probenum")
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    exit(1)
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def convertLine(x):
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    temp = x.split()
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    temp[1] = int(temp[1])
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    return tuple(temp)
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def probeBits( probe ):
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    str = ''
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    if (probe[1] > 1):
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        for i in range(probe[1]):
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            if i != (probe[1]-1):
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                str = str + f"{{{probe[0]}[{i}]}} "
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            else:
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                str = str + f"{{{probe[0]}[{i}]}} "
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    else:
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        str = f'{{{probe[0]}}}'
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    return str
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def printProbe( probe, i ):
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    bits = probeBits(probe)
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    print(bits)
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    return (
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        f'create_debug_port u_ila_0 probe\n'
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        f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
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        f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
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        f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
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    )
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def main(args):
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    if (len(args) != 3):
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        usage()
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    name = args[0]
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    width = int(args[1])
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    probeNum = int(args[2])
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    probe = (name, width)
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    print(printProbe(probe, probeNum))
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if __name__ == '__main__':
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    main(sys.argv[1:])
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