cvw/pipelined/regression
2022-01-28 14:37:15 -06:00
..
slack-notifier Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wave-dos Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
buildrootBugFinder.py Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
fpga-wave.do Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
lint-wally Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
linux-wave.do Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
make-tests.sh Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Makefile Fixed path to riscvOVPsimPlus 2022-01-21 00:12:14 +00:00
regression-wally Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
sim-buildroot Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-buildroot-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-coremark-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-wally LSU Cleanup 2022-01-15 01:11:17 +00:00
sim-wally-batch Renamed LSUStall to LSUStallM 2022-01-15 00:24:16 +00:00
wally-buildroot-batch.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-buildroot.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-coremark.do Improve wavefile by adding performance counters. 2022-01-12 10:53:29 -06:00
wally-fp64-batch.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-fp64.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-harvard.do Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-pipelined-fpga.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-pipelined-tim-batch.do Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
wally-pipelined-tim.do Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
wally-pipelined.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wave-all.do Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
wave-coremark.do Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
wave.do Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00