Rose Thompson dd3460c1a9 Fixed makefile and regression-wally so that code coverage now works.		2024-04-16 15:44:42 -05:00
..
bp-results	Updates to branch predictor collection.	2024-03-29 13:52:28 -05:00
questa	Fixed merge conflict bug in the last pull request.	2024-04-16 10:32:24 -05:00
slack-notifier	Renamed regression to sim	2023-02-02 14:48:23 -08:00
vcs	Reorganizing sim directory for multiple simulators	2024-04-05 18:19:46 -07:00
verilator	Merge branch 'verilator_getenv' into wsim_verilator	2024-04-12 15:27:09 -07:00
xcelium	Reorganizing sim directory for multiple simulators	2024-04-05 18:19:46 -07:00
bpred-sim.py	Changes to support concurrent simulation of all the branch predictor sweeps.	2023-11-26 22:19:34 -06:00
buildrootBugFinder.py	Renamed wally-piplined.do to wally.do	2023-02-04 04:38:41 -08:00
coverage	tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker	2023-09-02 12:56:36 -07:00
FPbuild.txt	Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file	2023-06-20 17:26:54 -05:00
imperas.ic	HPTW coverage improvements	2024-01-26 10:46:38 -08:00
make-tests.sh	Renamed regression to sim	2023-02-02 14:48:23 -08:00
Makefile	Fixed makefile and regression-wally so that code coverage now works.	2024-04-16 15:44:42 -05:00
makefile-memfile	Renamed regression to sim	2023-02-02 14:48:23 -08:00
run-imperasdv-tests.bash	Revert "Update for new layout of ImperasDV files"	2023-06-13 04:17:56 -07:00
rv64gc_CacheSim.py	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
test	Renamed regression to sim	2023-02-02 14:48:23 -08:00