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https://github.com/openhwgroup/cvw
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77 lines
3.0 KiB
Systemverilog
Executable File
77 lines
3.0 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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// fsgninj.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 6/23/2021
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//
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// Purpose: FPU Sign Injection instructions
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fsgninj import cvw::*; #(parameter cvw_t P) (
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input logic Xs, Ys, // X and Y sign bits
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input logic [P.FLEN-1:0] X, // X
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input logic [P.FMTBITS-1:0] Fmt, // format
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input logic [1:0] OpCtrl, // operation control
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output logic [P.FLEN-1:0] SgnRes // result
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);
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logic ResSgn; // result sign
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// OpCtrl:
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// 00 - fsgnj - directly copy over sign value of Y
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// 01 - fsgnjn - negate sign value of Y
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// 10 - fsgnjx - XOR sign values of X and Y
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// calculate the result's sign
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assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys;
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// format final result based on precision
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// - uses NaN-blocking format
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// - if there are any unused bits the most significant bits are filled with 1s
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if (P.FPSIZES == 1)
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assign SgnRes = {ResSgn, X[P.FLEN-2:0]};
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else if (P.FPSIZES == 2)
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assign SgnRes = {~Fmt|ResSgn, X[P.FLEN-2:P.LEN1], Fmt ? X[P.LEN1-1] : ResSgn, X[P.LEN1-2:0]};
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else if (P.FPSIZES == 3) begin
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logic [2:0] SgnBits;
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always_comb
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case (Fmt)
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P.FMT: SgnBits = {ResSgn, X[P.LEN1-1], X[P.LEN2-1]};
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P.FMT1: SgnBits = {1'b1, ResSgn, X[P.LEN2-1]};
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P.FMT2: SgnBits = {2'b11, ResSgn};
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default: SgnBits = {3{1'bx}};
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endcase
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assign SgnRes = {SgnBits[2], X[P.FLEN-2:P.LEN1], SgnBits[1], X[P.LEN1-2:P.LEN2], SgnBits[0], X[P.LEN2-2:0]};
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end else if (P.FPSIZES == 4) begin
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logic [3:0] SgnBits;
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always_comb
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case (Fmt)
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P.Q_FMT: SgnBits = {ResSgn, X[P.D_LEN-1], X[P.S_LEN-1], X[P.H_LEN-1]};
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P.D_FMT: SgnBits = {1'b1, ResSgn, X[P.S_LEN-1], X[P.H_LEN-1]};
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P.S_FMT: SgnBits = {2'b11, ResSgn, X[P.H_LEN-1]};
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P.H_FMT: SgnBits = {3'b111, ResSgn};
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endcase
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assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
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end
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endmodule
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