mirror of
https://github.com/openhwgroup/cvw
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93 lines
3.7 KiB
Systemverilog
93 lines
3.7 KiB
Systemverilog
///////////////////////////////////////////
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// triggergen.sv
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//
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// Written: Rose Thompson ross1728@gmail.com
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// Created: June 26, 2024
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// Modified: June 26, 2024
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//
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// Purpose: Scans for specific ethernet frame to generate an ila trigger.
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module triggergen import cvw::*; (
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input logic clk, reset,
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input logic [31:0] RvviAxiRdata,
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input logic [3:0] RvviAxiRstrb,
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input logic RvviAxiRlast,
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input logic RvviAxiRvalid,
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output logic IlaTrigger);
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typedef enum {STATE_RST, STATE_COMPARE, STATE_MISMATCH, STATE_TRIGGER, STATE_TRIGGER_DONE} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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logic [31:0] mem [4:0];
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logic [2:0] Counter;
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logic CounterEn, CounterRst;
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logic [31:0] RvviAxiRdataDelay;
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logic [3:0] RvviAxiRstrbDelay;
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logic RvviAxiRvalidDelay;
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logic Match, Overflow, Mismatch, Threshold;
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assign mem[0] = 32'h1111_6843; // dst mac [31:0]
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assign mem[1] = 32'h1654_4502; // src mac [15:0], dst mac [47:32]
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assign mem[2] = 32'h8f54_0000; // src mac [47:16]
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assign mem[3] = 32'h7274_005c; // "rt", ether type 005c
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assign mem[4] = 32'h6e69_6769; // "igin" (trigin)
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flopenr #(32) rvviaxirdatareg(clk, reset, RvviAxiRvalid, RvviAxiRdata, RvviAxiRdataDelay);
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flopenr #(4) rvviaxirstrbreg(clk, reset, RvviAxiRvalid, RvviAxiRstrb, RvviAxiRstrbDelay);
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flopr #(1) rvviaxirvalidreg(clk, reset, RvviAxiRvalid, RvviAxiRvalidDelay);
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counter #(3) counter(clk, CounterRst, CounterEn, Counter);
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always_ff @(posedge clk) begin
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if(reset) CurrState <= STATE_RST;
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else CurrState <= NextState;
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end
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always_comb begin
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case(CurrState)
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STATE_RST: if(RvviAxiRvalid) NextState = STATE_COMPARE;
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else NextState = STATE_RST;
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STATE_COMPARE: if(RvviAxiRlast) NextState = STATE_RST;
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else if(Mismatch | Overflow) NextState = STATE_MISMATCH;
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else if(Threshold & Match) NextState = STATE_TRIGGER;
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else NextState = STATE_COMPARE;
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STATE_MISMATCH: if(RvviAxiRlast) NextState = STATE_RST;
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else NextState = STATE_MISMATCH;
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STATE_TRIGGER: if(RvviAxiRlast) NextState = STATE_RST;
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else NextState = STATE_TRIGGER_DONE;
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STATE_TRIGGER_DONE: if(RvviAxiRlast) NextState = STATE_RST;
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else NextState = STATE_TRIGGER_DONE;
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default: NextState = STATE_RST;
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endcase
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end
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assign Match = (mem[Counter] == RvviAxiRdataDelay) & (CurrState == STATE_COMPARE) & RvviAxiRvalidDelay;
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assign Overflow = Counter > 4'd4;
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assign Threshold = Counter >= 4'd4;
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assign Mismatch = (mem[Counter] != RvviAxiRdataDelay) & (CurrState == STATE_COMPARE) & RvviAxiRvalidDelay;
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assign IlaTrigger = CurrState == STATE_TRIGGER;
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assign CounterRst = CurrState == STATE_RST;
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assign CounterEn = RvviAxiRvalid;
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endmodule
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