Rose Thompson a324e79b6f Updated the ethernet frame gap for a faster computer.		2024-07-19 13:12:13 -05:00
..
cache	Signal name changes to match book.	2024-06-02 16:32:25 -05:00
ebu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
fpu	Modify Fround Tmask to work for X=1	2024-05-25 12:56:02 -07:00
generic	Fixed byte enables for synthesis	2024-04-27 06:25:24 -07:00
hazard	Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.	2024-05-22 09:56:12 -05:00
ieu	AES cleanup	2024-05-24 14:28:30 -07:00
ifu	Last of the branch predictor signal name updates.	2024-06-02 17:01:51 -05:00
lsu	Changed name CacheWriteData to WriteData.	2024-05-28 18:00:39 -05:00
mdu	Remove additional bitwise operator	2024-05-15 09:29:54 -07:00
mmu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
privileged	Updated more signal names to match book.	2024-06-02 16:59:11 -05:00
rvvi	Updated the ethernet frame gap for a faster computer.	2024-07-19 13:12:13 -05:00
uncore	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
wally	Merge branch 'main' into rvvi	2024-06-10 18:10:23 -07:00
cvw.sv	Merge pull request #798 from jordancarlin/newConfig	2024-05-15 10:28:44 -05:00