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https://github.com/openhwgroup/cvw
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68 lines
2.5 KiB
Systemverilog
68 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// fclassivy.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Floating-point classify unit
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fclassify import cvw::*; #(parameter cvw_t P) (
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input logic Xs, // sign bit
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input logic XNaN, // is NaN
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input logic XSNaN, // is signaling NaN
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input logic XSubnorm, // is Subnormal
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input logic XZero, // is zero
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input logic XInf, // is infinity
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output logic [P.XLEN-1:0] ClassRes // classify result
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);
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logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal
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logic NInf, NZero, NNorm, NSubnorm; // is the input a negative infinity/zero/normal/subnormal
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logic XNorm; // is the input normal
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// determine the sub categories
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assign XNorm= ~(XNaN | XInf| XSubnorm| XZero);
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assign PInf = ~Xs&XInf;
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assign NInf = Xs&XInf;
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assign PNorm = ~Xs&XNorm;
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assign NNorm = Xs&XNorm;
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assign PSubnorm = ~Xs&XSubnorm;
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assign NSubnorm = Xs&XSubnorm;
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assign PZero = ~Xs&XZero;
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assign NZero = Xs&XZero;
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// determine sub category and combine into the result
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// bit 0 - -Inf
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// bit 1 - -Norm
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// bit 2 - -Subnorm
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// bit 3 - -Zero
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// bit 4 - +Zero
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// bit 5 - +Subnorm
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// bit 6 - +Norm
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// bit 7 - +Inf
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// bit 8 - signaling NaN
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// bit 9 - quiet NaN
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assign ClassRes = {{P.XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PSubnorm, PZero, NZero, NSubnorm, NNorm, NInf};
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endmodule
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