Ross Thompson 5726b5b640 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.		2022-01-13 22:21:43 -06:00
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BTBPredictor.txt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
twoBitPredictor.txt	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-config.vh	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00