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https://github.com/openhwgroup/cvw
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110 lines
5.0 KiB
Systemverilog
110 lines
5.0 KiB
Systemverilog
///////////////////////////////////////////
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// tlbcamline.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// Implemented SV48 on top of SV39. This included adding SvMode input signal and the wally constants
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// Mostly this was done to make the PageNumberMixer work.
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//
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// Purpose: CAM line for the translation lookaside buffer (TLB)
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// Determines whether a virtual page number matches the stored key.
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module tlbcamline import cvw::*; #(parameter cvw_t P,
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parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
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input logic clk, reset,
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input logic [P.VPN_BITS-1:0] VPN, // The requested page number to compare against the key
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input logic [P.ASID_BITS-1:0] SATP_ASID,
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input logic SV39Mode,
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input logic WriteEnable, // Write a new entry to this line
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input logic PTE_G,
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input logic PTE_NAPOT, // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
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input logic [1:0] PageTypeWriteVal,
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input logic TLBFlush, // Flush this line (set valid to 0)
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output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one?
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output logic Match
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);
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// PageTypeRead is a key for a tera, giga, mega, or kilopage.
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// PageType == 2'b00 --> kilopage
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// PageType == 2'b01 --> megapage
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// PageType == 2'b10 --> gigapage
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// PageType == 2'b11 --> terapage
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// This entry has KEY_BITS for the key plus one valid bit.
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logic Valid;
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logic [KEY_BITS-1:0] Key;
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logic [1:0] PageType;
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// Split up key and query into sections for each page table level.
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logic [P.ASID_BITS-1:0] Key_ASID;
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logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1;
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logic MatchASID, Match0, Match1;
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assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G;
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if (P.XLEN == 32) begin: match
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assign {Key_ASID, Key1, Key0} = Key;
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assign {Query1, Query0} = VPN;
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// Calculate the actual match value based on the input vpn and the page type.
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// For example, a megapage in SV32 only cares about VPN[1], so VPN[0]
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// should automatically match.
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assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section
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assign Match1 = (Query1 == Key1);
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assign Match = Match0 & Match1 & MatchASID & Valid;
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end else begin: match
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logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
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logic Match2, Match3, MatchNAPOT;
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assign {Query3, Query2, Query1, Query0} = VPN;
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assign {Key_ASID, Key3, Key2, Key1, Key0} = Key;
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// Calculate the actual match value based on the input vpn and the page type.
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// For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1]
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// should automatically match.
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// In Svnapot, if N bit is set and bottom 4 bits of PPN = 1000, then these bits don't need to match
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assign MatchNAPOT = P.SVNAPOT_SUPPORTED & PTE_NAPOT & (Query0[SEGMENT_BITS-1:4] == Key0[SEGMENT_BITS-1:4]);
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assign Match0 = (Query0 == Key0) | (PageType > 2'd0) | MatchNAPOT; // least significant section
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assign Match1 = (Query1 == Key1) | (PageType > 2'd1);
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assign Match2 = (Query2 == Key2) | (PageType > 2'd2);
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assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used
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assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
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end
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// On a write, update the type of the page referred to by this line.
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flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType);
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assign PageTypeRead = PageType & {2{Match}};
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// On a write, set the valid bit high and update the stored key.
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// On a flush, zero the valid bit and leave the key unchanged.
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// *** Might we want to update stored key right away to output match on the
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// write cycle? (using a mux)
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flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid);
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flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
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endmodule
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