Noah Boorstin c03f69fb80 Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.		2021-02-04 22:03:45 +00:00
..
csr.sv	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
csrc.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
csri.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
csrm.sv	Change CSR reset and available bits to conform to OVPsim	2021-02-04 22:03:45 +00:00
csrn.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
csrs.sv	Change CSR reset and available bits to conform to OVPsim	2021-02-04 22:03:45 +00:00
csrsr.sv	Change CSR reset and available bits to conform to OVPsim	2021-02-04 22:03:45 +00:00
csru.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
privdec.sv	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
privileged.sv	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
trap.sv	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00