slmnemo beb4317e68 Added comments to signals added so the bus is easier to analyze		2022-06-10 20:30:04 -07:00
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cache
ebu	Passed Regression: Seems to work perfectly fine	2022-06-09 18:21:13 -07:00
fpu	fma synth warnings and errors removed	2022-06-06 16:06:04 +00:00
generic	Cleaned bram interface	2022-06-08 01:39:44 +00:00
hazard	added #1 delays to Stalls and Flushes in hazard unit	2022-06-08 16:28:09 +00:00
ieu	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
ifu	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
lsu	Added comments to signals added so the bus is easier to analyze	2022-06-10 20:30:04 -07:00
mmu
muldiv
ppa	added one bit muxes for data critical synths	2022-06-09 00:06:12 +00:00
privileged
uncore	Fixed lint error	2022-06-09 17:22:04 -07:00
wally	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
sdc