Rose Thompson 84d86b1994 Fixed spill bugs in the aligner.		2023-11-10 17:18:45 -06:00
..
cache	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
ebu	Merge branch 'main' into Zicclsm	2023-11-02 12:55:51 -05:00
fpu	Reparitioned sign logic in fdivsqrt to match paper	2023-11-06 14:11:42 -08:00
generic	set default USE_SRAM=0 in memories; cleaned up synthesis script grep for cvw_t	2023-11-03 06:37:05 -07:00
hazard	Cleaned up the implementation changes for wfi.	2023-10-24 23:11:48 -05:00
ieu	minfo test working again with mconfigptr for RV64	2023-10-15 06:41:52 -07:00
ifu	Modified rams to take USE_SRAM rather than P to facilitate synthesis	2023-11-03 05:44:13 -07:00
lsu	Fixed spill bugs in the aligner.	2023-11-10 17:18:45 -06:00
mdu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-06-15 15:38:38 -05:00
mmu	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00
privileged	Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder.	2023-10-30 09:56:17 -07:00
uncore	Cleanup	2023-11-09 16:52:55 -08:00
wally	harris code review 3	2023-11-01 10:14:15 -07:00
cvw.sv	Merge branch 'main' into Zicclsm	2023-11-10 16:15:32 -06:00