cvw/pipelined/src
2022-12-30 18:41:40 -08:00
..
cache Minor optimizations. 2022-12-23 20:11:36 -06:00
ebu Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
fpu various formatting fixes and comments 2022-12-30 18:41:40 -08:00
generic Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
hazard Minor optimizations. 2022-12-23 20:11:36 -06:00
ieu ALU cleanup 2022-12-24 07:18:35 -08:00
ifu Cleanup spill logic. 2022-12-30 14:59:51 -06:00
lsu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
mdu Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
mmu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
ppa
privileged Signal renames for PC*NextF and SelSpillNextF. 2022-12-30 14:21:20 -06:00
uncore Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 2022-12-21 09:00:09 -06:00
wally Signal renames for PC*NextF and SelSpillNextF. 2022-12-30 14:21:20 -06:00
sdc