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slack-notifier
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added instructions to slack notifier
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2022-05-18 16:50:31 -07:00 |
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wave-dos
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Added signal to monitor HBURST and comments for each burst in busdp
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2022-05-26 13:35:49 -07:00 |
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wkdir
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added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
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2022-05-17 20:32:38 +00:00 |
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buildrootBugFinder.py
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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fpga-wave.do
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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lint-wally
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removed rv64fp from lint
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2022-06-21 15:48:47 -07:00 |
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linux-wave.do
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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make-tests.sh
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simplified make-tests.sh to run the current makefile in regression
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2022-05-17 17:29:34 -07:00 |
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Makefile
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changed order of makefiles and fixed warnings when running makes
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2022-06-21 16:10:18 -07:00 |
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makefile-memfile
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fixed issue where the unused spike elf files were being used to find objdump files that didn't exist causing makefile-memfile to fail prematurely
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2022-06-21 15:39:04 -07:00 |
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regression-wally
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./regression-wally -buildroot or ./regression-wally -all now builds Linux from instruction 0 instead of trying to reach instruction 246000000
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2022-06-29 13:40:11 -07:00 |
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sim-buildroot
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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sim-buildroot-batch
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sim-buildroot-batch now runs wally-pipelined-batch
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2022-07-06 18:06:43 -07:00 |
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sim-testfloat
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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sim-testfloat-batch
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modified result select to account for x/inf
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2022-06-24 21:23:15 +00:00 |
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sim-wally
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qslc_r4a2 generator
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2022-06-09 17:26:47 +00:00 |
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sim-wally-batch
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Fixed unpacker bug LT EQ LE pass testfloat
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2022-05-20 17:19:50 +00:00 |
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testfloat.do
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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wally-harvard.do
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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wally-pipelined-batch.do
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sim-buildroot-batch now runs wally-pipelined-batch
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2022-07-06 18:06:43 -07:00 |
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wally-pipelined-fpga.do
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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wally-pipelined.do
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Added check to halt testbench on failing to find file
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2022-07-05 02:28:59 +00:00 |
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wave-all.do
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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wave-fpu.do
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variable interations implemented in radix-4 divider
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2022-07-11 18:30:21 -07:00 |
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wave.do
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Merge branch 'main' into cacheburstmode
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2022-06-09 17:51:03 -07:00 |
