mirror of
https://github.com/openhwgroup/cvw
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90 lines
3.1 KiB
Python
Executable File
90 lines
3.1 KiB
Python
Executable File
#!/usr/bin/env python3
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###########################################
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## CacheSimTest.py
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##
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## Written: lserafini@hmc.edu
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## Created: 4 April 2023
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## Modified: 5 April 2023
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##
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## Purpose: Confirm that the cache simulator behaves as expected.
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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## https://github.com/openhwgroup/cvw
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https:##solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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import sys
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import os
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sys.path.append(os.path.expanduser("~/cvw/bin"))
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import CacheSim as cs
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if __name__ == "__main__":
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cache = cs.Cache(16, 4, 16, 8)
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# 0xABCD -> tag: AB, set: C, offset: D
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#address split checking
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assert (cache.splitaddr(0x1234) == (0x12,0x3,0x4))
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assert (cache.splitaddr(0x2638) == (0x26,0x3,0x8))
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assert (cache.splitaddr(0xA3E6) == (0xA3,0xE,0x6))
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#insert way 0 set C tag AB
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assert (cache.cacheaccess(0xABCD) == 'M')
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assert (cache.ways[0][0xC].tag == 0xAB)
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assert (cache.cacheaccess(0xABCD) == 'H')
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assert (cache.pLRU[0xC] == [1,1,0])
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#make way 0 set C dirty
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assert (cache.cacheaccess(0xABCD, True) == 'H')
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#insert way 1 set C tag AC
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assert (cache.cacheaccess(0xACCD) == 'M')
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assert (cache.ways[1][0xC].tag == 0xAC)
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assert (cache.pLRU[0xC] == [1,0,0])
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#insert way 2 set C tag AD
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assert (cache.cacheaccess(0xADCD) == 'M')
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assert (cache.ways[2][0xC].tag == 0xAD)
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assert (cache.pLRU[0xC] == [0,0,1])
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#insert way 3 set C tag AE
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assert (cache.cacheaccess(0xAECD) == 'M')
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assert (cache.ways[3][0xC].tag == 0xAE)
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assert (cache.pLRU[0xC] == [0,0,0])
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#misc hit and pLRU checking
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assert (cache.cacheaccess(0xABCD) == 'H')
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assert (cache.pLRU[0xC] == [1,1,0])
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assert (cache.cacheaccess(0xADCD) == 'H')
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assert (cache.pLRU[0xC] == [0,1,1])
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#evict way 1, now set C has tag AF
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assert (cache.cacheaccess(0xAFCD) == 'E')
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assert (cache.ways[1][0xC].tag == 0xAF)
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assert (cache.pLRU[0xC] == [1,0,1])
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#evict way 3, now set C has tag AC
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assert (cache.cacheaccess(0xACCD) == 'E')
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assert (cache.ways[3][0xC].tag == 0xAC)
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assert (cache.pLRU[0xC] == [0,0,0])
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#evict way 0, now set C has tag EA
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#this line was dirty, so there was a wb
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assert (cache.cacheaccess(0xEAC2) == 'D')
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assert (cache.ways[0][0xC].tag == 0xEA)
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assert (cache.pLRU[0xC] == [1,1,0]) |