cvw/wally-pipelined/src/uncore
2021-07-04 11:39:59 -04:00
..
clint.sv Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
dtim.sv Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
gpio.sv Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
plic.sv peripheral lint fixes 2021-06-10 10:19:10 -04:00
subwordwrite.sv Data memory bus integration 2021-02-07 23:21:55 -05:00
uart.sv rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
uartPC16550D.sv Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
uncore.sv Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00