David Harris b59213c83f Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders		2021-07-04 16:33:13 -04:00
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cache	src/cache/ICacheCntrl.sv	2021-07-03 11:24:41 -05:00
ebu	Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker	2021-07-03 03:29:33 -04:00
fpu	Commented out some unused modules	2021-07-04 01:40:27 -04:00
generic	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00
hazard	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ieu	Merge branch 'main' into bigbadbranch	2021-07-02 11:52:26 -05:00
ifu	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00
lsu	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00
mmu	Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders	2021-07-04 16:33:13 -04:00
muldiv	Commented out some unused modules	2021-07-04 01:40:27 -04:00
privileged	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00
uncore	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
wally	Fixed MPRV and MXR checks in TLB	2021-07-04 13:20:29 -04:00