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csrwrites.S
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dcache1.py
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Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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2023-04-19 01:34:01 -07:00 |
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dcache1.S
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Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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2023-04-19 01:34:01 -07:00 |
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dcache2.S
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add D$ test case to trigger a FlushStage while SetDirtyWay=1
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2023-04-19 01:34:01 -07:00 |
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ebu.S
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fpu.S
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Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
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2023-04-22 12:22:45 -07:00 |
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ieu.S
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ifu.S
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ifuCamlineWrite.S
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Increase of TLB coverage in IFU
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2023-04-17 18:35:03 -07:00 |
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lsu.S
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add back K. Box and M. Cook Lsu test
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2023-04-13 17:50:18 -07:00 |
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Makefile
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pmp.S
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pmpadrdecs.S
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Pmpadrdecs test cases changing AdrMode to 2 or 3
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2023-04-27 12:23:35 -07:00 |
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pmpcfg1.S
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Add test cases for pmpcfg.S
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2023-04-18 23:06:52 -07:00 |
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pmpcfg2.S
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Add test cases for pmpcfg.S
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2023-04-18 23:06:52 -07:00 |
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pmpcfg.S
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pmpaddr0 and pmpaddr2 test cases
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2023-04-25 15:37:04 -07:00 |
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pmppriority.S
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added tests for pmppriority module
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2023-04-27 16:12:43 -07:00 |
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priv.S
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Excluded and added coverage for WFI test case.
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2023-04-25 17:06:57 -07:00 |
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tlbASID.S
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Update tlbASID.S
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2023-04-27 14:32:57 -07:00 |
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tlbGLB.S
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Comment tlbGBL more discriptively
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2023-05-04 19:13:47 -05:00 |
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tlbGP.S
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complete camline coverage on IFU and LSU
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2023-04-27 14:26:10 -07:00 |
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tlbKP.S
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update tests.vh, add tlbKP to load all lines of tlb
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2023-04-13 15:13:55 -07:00 |
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tlbM3.S
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Add in a test that makes match 3 = 0 for all tlb lines
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2023-04-20 14:50:06 -07:00 |
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tlbMP.S
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complete camline coverage on IFU and LSU
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2023-04-27 14:26:10 -07:00 |
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tlbTP.S
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complete camline coverage on IFU and LSU
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2023-04-27 14:26:10 -07:00 |
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vm64check.S
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WALLY-init-lib.h
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Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
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2023-04-22 12:22:45 -07:00 |
