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57 lines
2.5 KiB
Systemverilog
57 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// tlblru.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Implementation of bit pseudo least-recently-used algorithm for
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// cache evictions. Outputs the index of the next entry to be written.
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module tlblru #(parameter TLB_ENTRIES = 8) (
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input logic clk, reset,
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input logic TLBWrite,
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input logic TLBFlush,
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input logic [TLB_ENTRIES-1:0] Matches,
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input logic CAMHit,
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output logic [TLB_ENTRIES-1:0] WriteEnables
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);
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logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
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logic [TLB_ENTRIES-1:0] WriteLines;
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logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
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logic AllUsed; // High if the next access causes all RU bits to be 1
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// Find the first line not recently used
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priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));
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// Track recently used lines, updating on a CAM Hit or TLB write
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assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
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assign AccessLines = TLBWrite ? WriteLines : Matches;
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assign RUBitsAccessed = AccessLines | RUBits;
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assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
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assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
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// enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
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flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
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endmodule
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