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50 lines
1.7 KiB
Systemverilog
50 lines
1.7 KiB
Systemverilog
///////////////////////////////////////////
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// or_rows.sv
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//
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// Written: David_Harris@hmc.edu 13 July 2021
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// Modified:
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//
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// Purpose: Perform OR across a 2-dimensional array of inputs to produce a 1-D array of outputs
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// perform an OR of all the rows in an array, producing one output for each column
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// equivalent to assign y = a.or
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module or_rows #(parameter ROWS = 8, COLS=2) (
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input var logic [COLS-1:0] a[ROWS-1:0],
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output logic [COLS-1:0] y
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);
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genvar row;
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if(ROWS == 1)
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assign y = a[0];
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else begin
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/* verilator lint_off UNOPTFLAT */
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logic [COLS-1:0] mid[ROWS-1:1];
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assign mid[1] = a[0] | a[1];
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for (row=2; row < ROWS; row++)
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assign mid[row] = mid[row-1] | a[row];
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assign y = mid[ROWS-1];
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/* verilator lint_on UNOPTFLAT */
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end
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endmodule
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