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fdivsqrt.sv
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Added conditional OTFC swap for simplified int postprocessing
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2022-11-06 23:09:09 +00:00 |
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fdivsqrtfgen2.sv
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renamed q to u for unified digit selection
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2022-09-20 04:35:14 -07:00 |
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fdivsqrtfgen4.sv
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renamed u to udigit to avoid conflict with U
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2022-09-20 19:29:23 -07:00 |
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fdivsqrtfsm.sv
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Adding start signals for integer divider to fdivsqrt
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2022-09-29 16:30:25 -07:00 |
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fdivsqrtiter.sv
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propagated otfc swap to Rad2 and 4 qslc
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2022-11-06 23:32:38 +00:00 |
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fdivsqrtpostproc.sv
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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fdivsqrtpreproc.sv
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Added conditional OTFC swap for simplified int postprocessing
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2022-11-06 23:09:09 +00:00 |
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fdivsqrtqsel2.sv
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propagated otfc swap to Rad2 and 4 qslc
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2022-11-06 23:32:38 +00:00 |
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fdivsqrtqsel4.sv
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New fdivsqrtqsel4cmp module based on comparators rather than table lookup
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2022-10-09 04:47:44 -07:00 |
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fdivsqrtqsel4cmp.sv
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propagated otfc swap to Rad2 and 4 qslc
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2022-11-06 23:32:38 +00:00 |
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fdivsqrtstage2.sv
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propagated otfc swap to Rad2 and 4 qslc
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2022-11-06 23:32:38 +00:00 |
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fdivsqrtstage4.sv
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propagated otfc swap to Rad2 and 4 qslc
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2022-11-06 23:32:38 +00:00 |
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fdivsqrtuotfc2.sv
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renamed q to u for unified digit selection
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2022-09-20 04:35:14 -07:00 |
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fdivsqrtuotfc4.sv
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renamed u to udigit to avoid conflict with U
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2022-09-20 19:29:23 -07:00 |
