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205 lines
8.8 KiB
Systemverilog
205 lines
8.8 KiB
Systemverilog
///////////////////////////////////////////
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// abhmultimanager
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//
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// Written: Ross Thompson August 29, 2022
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// ross1728@gmail.com
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// Modified:
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//
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// Purpose: AHB multi manager interface to merge LSU and IFU controls.
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// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
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// Arbitrates requests from instruction and data streams
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// Connects core to peripherals and I/O pins on SOC
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// Bus width presently matches XLEN
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// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbmultimanager
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(
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input logic clk, reset,
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// Signals from IFU
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input logic [`PA_BITS-1:0] IFUHADDR,
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input logic [2:0] IFUHBURST,
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input logic [1:0] IFUHTRANS,
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output logic IFUHREADY,
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// Signals from LSU
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input logic [`PA_BITS-1:0] LSUHADDR,
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input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN
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input logic [`XLEN/8-1:0] LSUHWSTRB,
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input logic [2:0] LSUHSIZE,
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input logic [2:0] LSUHBURST,
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input logic [1:0] LSUHTRANS,
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input logic LSUHWRITE,
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output logic LSUHREADY,
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// add LSUHWSTRB ***
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// AHB-Lite external signals
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(* mark_debug = "true" *) input logic HREADY, HRESP,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [3:0] HPROT,
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(* mark_debug = "true" *) output logic [1:0] HTRANS,
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(* mark_debug = "true" *) output logic HMASTLOCK
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);
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localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator
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typedef enum logic [1:0] {IDLE, ARBITRATE} statetype;
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statetype CurrState, NextState;
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logic LSUGrant;
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logic [ADRBITS-1:0] HADDRD;
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logic [1:0] HSIZED;
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logic [1:0] save, restore, dis, sel;
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logic both;
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logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDROut;
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logic [1:0] IFUHTRANSSave, IFUHTRANSOut;
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logic [2:0] IFUHBURSTSave, IFUHBURSTOut;
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logic [2:0] IFUHSIZEOut;
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logic IFUHWRITEOut;
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logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDROut;
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logic [1:0] LSUHTRANSSave, LSUHTRANSOut;
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logic [2:0] LSUHBURSTSave, LSUHBURSTOut;
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logic [2:0] LSUHSIZESave, LSUHSIZEOut;
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logic LSUHWRITESave, LSUHWRITEOut;
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logic IFUReq, LSUReq;
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logic IFUActive, LSUActive;
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logic BeatCntEn;
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logic [4-1:0] NextBeatCount, BeatCount, BeatCountDelayed;
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logic FinalBeat;
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic [3:0] Threshold;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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// if two requests come in at once pick one to select and save the others Address phase
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// inputs. Abritration scheme is LSU always goes first.
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// input stage IFU
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managerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
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.Request(IFUReq), .Active(IFUActive),
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.HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
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.HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
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.HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
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// input stage LSU
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managerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
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.Request(LSUReq), .Active(LSUActive),
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.HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
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.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
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.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
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// output mux //*** rewrite for general number of managers.
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assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0;
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assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits
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assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
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assign HTRANS = sel[1] ? LSUHTRANSOut : sel[0] ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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assign HWRITE = sel[1] ? LSUHWRITEOut : sel[0] ? 1'b0 : '0;
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assign HPROT = 4'b0011; // not used; see Section 3.7
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assign HMASTLOCK = 0; // no locking supported
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// data phase muxing. This would be a mux if IFU wrote data.
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assign HWDATA = LSUHWDATA;
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assign HWSTRB = LSUHWSTRB;
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// HRDATA is sent to all managers at the core level.
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// FSM decides if arbitration needed. Arbitration is held until the last beat of
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// a burst is completed.
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assign both = LSUActive & IFUActive;
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flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
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always_comb
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case (CurrState)
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeat & ~(LSUReq & IFUReq)) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase
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// This part is only used when burst mode is supported.
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// Manager needs to count beats.
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flopenr #(4)
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BeatCountReg(.clk(HCLK),
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.reset(~HRESETn | CntReset | FinalBeat),
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.en(BeatCntEn),
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.d(NextBeatCount),
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.q(BeatCount));
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// Used to store data from data phase of AHB.
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flopenr #(4)
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BeatCountDelayedReg(.clk(HCLK),
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.reset(~HRESETn | CntReset),
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.en(BeatCntEn),
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.d(BeatCount),
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.q(BeatCountDelayed));
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assign NextBeatCount = BeatCount + 1'b1;
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assign CntReset = NextState == IDLE;
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assign FinalBeat = (BeatCountDelayed == Threshold); // Detect when we are waiting on the final access.
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assign BeatCntEn = (NextState == ARBITRATE & HREADY);
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logic [2:0] HBURSTD;
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flopenr #(3) HBURSTReg(.clk(HCLK), .reset(~HRESETn), .en(HTRANS == 2'b10), .d(HBURST), .q(HBURSTD));
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// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
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always_comb begin
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case(HBURSTD)
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0: Threshold = 4'b0000;
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3: Threshold = 4'b0011; // INCR4
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5: Threshold = 4'b0111; // INCR8
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7: Threshold = 4'b1111; // INCR16
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default: Threshold = 4'b0000; // INCR without end.
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endcase
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end
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// end of burst mode.
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// basic arb always selects LSU when both
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// replace this block for more sophisticated arbitration as needed.
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// Manager 0 (IFU)
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assign save[0] = CurrState == IDLE & both;
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assign restore[0] = CurrState == ARBITRATE;
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assign dis[0] = CurrState == ARBITRATE;
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assign sel[0] = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
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// Manager 1 (LSU)
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assign save[1] = 1'b0;
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assign restore[1] = 1'b0;
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assign dis[1] = 1'b0;
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assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
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endmodule
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