Rose Thompson 54c1d28c8b Fixed missing case in the align AccesByteOffset Mux.		2024-03-06 15:43:55 -06:00
..
cache	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-03-06 15:35:34 -06:00
ebu	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
fpu	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
generic	Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places	2024-03-06 11:02:04 -08:00
hazard	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
ieu	Changed '0 to 0 where possible per Chapter 4 style guidelines	2024-03-06 05:48:17 -08:00
ifu	Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur."	2024-03-06 15:16:37 -06:00
lsu	Fixed missing case in the align AccesByteOffset Mux.	2024-03-06 15:43:55 -06:00
mdu	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
mmu	Revert "Non-ideal fix. Added new output from pma which indicates if the write shift should occur."	2024-03-06 15:16:37 -06:00
privileged	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-03-06 15:35:34 -06:00
uncore	Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places	2024-03-06 11:02:04 -08:00
wally	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-01-31 13:12:32 -06:00
cvw.sv	Fixed some lint errors in derived configs	2024-01-31 11:39:59 -08:00