mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
ae0cc085b4
1: It simplifies the interactions between the caches and the hptw. 2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process. There are two downsides. 1: Pollute the TLBs with not very relavent translations 2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop for each TLB line. |
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|---|---|---|
| .. | ||
| adrdec.sv | ||
| adrdecs.sv | ||
| decoder.sv | ||
| hptw.sv | ||
| mmu.sv | ||
| pmachecker.sv | ||
| pmpadrdec.sv | ||
| pmpchecker.sv | ||
| priorityonehot.sv | ||
| prioritythermometer.sv | ||
| tlb.sv | ||
| tlbcam.sv | ||
| tlbcamline.sv | ||
| tlbcontrol.sv | ||
| tlblru.sv | ||
| tlbmixer.sv | ||
| tlbram.sv | ||
| tlbramline.sv | ||