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https://github.com/openhwgroup/cvw
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108 lines
3.6 KiB
Systemverilog
108 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// globalHistoryPredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module globalHistoryPredictor
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#(parameter int k = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
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input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] Prediction,
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// update
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input logic [`XLEN-1:0] UpdatePC,
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input logic UpdateEN, PCSrcE,
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input logic [1:0] UpdatePrediction
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);
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logic [k-1:0] GHRF, GHRFNext;
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assign GHRFNext = {PCSrcE, GHRF[k-1:1]};
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flopenr #(k) GlobalHistoryRegister(.clk(clk),
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.reset(reset),
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.en(UpdateEN),
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.d(GHRFNext),
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.q(GHRF));
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logic [1:0] PredictionMemory;
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logic DoForwarding, DoForwardingF;
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logic [1:0] UpdatePredictionF;
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// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
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// GHR referes to the address that the past k branches points to in the prediction stage
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// GHRE refers to the address that the past k branches points to in the exectution stage
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SRAM2P1R1W #(k, 2) PHT(.clk(clk),
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.reset(reset),
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.RA1(GHRF),
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.RD1(PredictionMemory),
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.REN1(~StallF),
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.WA1(GHRFNext),
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.WD1(UpdatePrediction),
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.WEN1(UpdateEN),
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.BitWEN1(2'b11));
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// need to forward when updating to the same address as reading.
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// first we compare to see if the update and lookup addreses are the same
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assign DoForwarding = GHRF == GHRFNext;
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// register the update value and the forwarding signal into the Fetch stage
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// TODO: add stall logic ***
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flopr #(1) DoForwardingReg(.clk(clk),
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.reset(reset),
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.d(DoForwarding),
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.q(DoForwardingF));
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flopr #(2) UpdatePredictionReg(.clk(clk),
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.reset(reset),
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.d(UpdatePrediction),
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.q(UpdatePredictionF));
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assign Prediction = DoForwardingF ? UpdatePredictionF : PredictionMemory;
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//pipeline for GHR
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/*flopenrc #(k) GHRDReg(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(FlushD),
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.d(GHRF),
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.q(GHRD));
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flopenrc #(k) GHREReg(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.clear(FlushE),
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.d(GHRD),
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.q(GHRE));
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*/
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endmodule
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