cvw/testbench/common
Rose Thompson a8ab3c8342 Ok that is a stange bug.
The testbench used logic for the shadow ram, but the memory used bit. This caused questa to allocate huge amounts of memory and crash. Changing shadow ram to bit fixed the issue.
2023-12-20 12:25:34 -06:00
..
checksignature.sv Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
DCacheFlushFSM.sv Ok that is a stange bug. 2023-12-20 12:25:34 -06:00
functionName.sv Cleanup. 2023-12-18 16:38:56 -06:00
instrNameDecTB.sv Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
instrTrackerTB.sv moved riscvassertons to its own file, added proper license headers to testbench support files 2023-02-16 19:40:27 -08:00
loggers.sv Fixed Linux makefile; load branch predictor RAMs at startup for sim; fixed comment in trap; starting to make testbench more compatible with Verilator 2023-12-13 11:33:59 -08:00
ramxdetector.sv Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
riscvassertions.sv Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
wallyTracer.sv Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support 2023-11-23 20:36:45 -08:00
watchdog.sv Fixed regression error of watchdog timeout when PCM is optimized out of the IFU 2023-11-03 04:38:27 -07:00