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			62 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Markdown
		
	
	
	
	
	
			
		
		
	
	
			62 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Markdown
		
	
	
	
	
	
| Synthesis for RISC-V Microprocessor System-on-Chip Design
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| 
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| This subdirectory contains synthesis scripts for use with Synopsys
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| (snps) Design Compiler (DC).  Synthesis commands are found in
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| scripts/synth.tcl.
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| 
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| Example Usage
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| make synth DESIGN=wallypipelinedcore FREQ=500 CONFIG=rv32e
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| 
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| environment variables
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| 
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| DESIGN
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|         Design provides the name of the output log.  Default is synth.
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| 
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| FREQ
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|         Frequency in MHz.  Default is 500
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| 
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| CONFIG
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|         The Wally configuration file.  The default is rv32e.
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|         Examples: rv32e, rv64gc, rv32gc
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| 
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| TECH
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|         The target standard cell library.  The default is sky130.
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|         sky90: skywater 90nm TT 25C
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|         sky130: skywater 130nm TT 25C
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| 
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| SAIFPOWER
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|         Controls if power analysis is driven by switching factor or
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| 	RTL modelsim simulation. When enabled requires a saif file
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| 	named power.saif.  The default is 0.
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|         0: switching factor power analysis
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|         1: RTL simulation driven power analysis.
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| 
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| -----
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| Extra Tool (PPA)
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| 
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| To run ppa analysis that hones into target frequency, you can type:
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| python3 ppa/ppaSynth.py from the synthDC directory.  This runs a sweep
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| across all modules listed at the bottom of the ppaSynth.py file.
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| 
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| Two options for running the sweep.  The first run runs all modules for
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| all techs around a given frequency (i.e., freqs).  The second option
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| will run all designs for the specific module based on bestSynths.csv
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| values.   Since the second option is 2nd, it has priority.  If the
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| second set of values is commented out, it will run all widths.
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| 
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| WARNING:  The first option may runs lots of runs that could expend all
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| the licenses available for a license.  Therefore, care must be taken
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| to be sure that enough licenses are available for this first option.
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| 
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| ##### Run specific syntheses
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| 	widths = [8, 16, 32, 64, 128] 
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| 	modules = ['mul', 'adder', 'shifter', 'flop', 'comparator', 'binencoder', 'csa', 'mux2', 'mux4', 'mux8']
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| 	techs = ['sky90', 'sky130', 'tsmc28', 'tsmc28psyn']
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| 	freqs = [5000]
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| 	synthsToRun = allCombos(widths, modules, techs, freqs)
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| 
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| ##### Run a sweep based on best delay found in existing syntheses
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| 	module = 'adder'
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| 	width = 32
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| 	tech = 'tsmc28psyn'
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|  	synthsToRun = freqSweep(module, width, tech) |