cvw/pipelined/src/fpu
2022-07-19 00:04:24 +00:00
..
cvtshiftcalc.sv Rewrote convert shift calculation with always for ease of reading 2022-07-17 16:40:58 +00:00
divshiftcalc.sv renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
divsqrt.sv merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
fclassify.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
fcmp.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
fctrl.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
fcvt.sv renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
fhazard.sv postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
flags.sv removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
fma.sv moved Ss to execute stage 2022-07-18 20:48:56 +00:00
fmashiftcalc.sv reworked fmashiftcalc to match book 2022-07-19 00:04:24 +00:00
fpu.sv moved Ss to execute stage 2022-07-18 20:48:56 +00:00
fregfile.sv paramerterized some small fma units 2022-06-01 23:34:29 +00:00
fsgninj.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
negateintres.sv renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
normshift.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
otfc.sv forgot some files 2022-07-15 21:42:45 +00:00
postprocess.sv moved Ss to execute stage 2022-07-18 20:48:56 +00:00
qsel.sv forgot some files 2022-07-15 21:42:45 +00:00
resultsign.sv renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
round.sv renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
roundsign.sv moved Ss to execute stage 2022-07-18 20:48:56 +00:00
shiftcorrection.sv renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00
specialcase.sv forgot a file 2022-07-11 18:31:51 -07:00
srt.sv forgot some files 2022-07-15 21:42:45 +00:00
srtfsm.sv merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
srtpreproc.sv merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
unpack.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00
unpackinput.sv srt divider merged into fpu 2022-07-07 16:01:33 -07:00