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71 lines
2.2 KiB
Systemverilog
71 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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// mux.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Various flavors of multiplexers
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off DECLFILENAME */
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module mux3 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? d2 : (s[0] ? d1 : d0);
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endmodule
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module mux4 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
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endmodule
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module mux5 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3, d4,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[2] ? d4 : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
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endmodule
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module mux6 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
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input logic [2:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
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endmodule
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/* verilator lint_on DECLFILENAME */
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