mirror of
https://github.com/openhwgroup/cvw
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152 lines
6.9 KiB
Systemverilog
152 lines
6.9 KiB
Systemverilog
///////////////////////////////////////////
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// DCacheFlushFSM.sv
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//
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// Written: David Harris David_Harris@hmc.edu and Rose Thompson rose@rosethompson.net
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// Modified: 14 June 2023
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//
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// Purpose: The L1 data cache and any feature L2 or high cache will not necessary writeback all dirty
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// line before the end of test. Signature based regression tests need to check the L1 data cache
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// in addition to the main memory. These modules create a shadow memory with a projection of the
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// D$ contents.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
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(input logic clk,
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input logic start,
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output logic done);
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genvar adr;
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logic [P.XLEN-1:0] ShadowRAM[P.UNCORE_RAM_BASE>>(1+P.XLEN/32):(P.UNCORE_RAM_RANGE+P.UNCORE_RAM_BASE)>>1+(P.XLEN/32)];
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logic startD;
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if(P.DCACHE_SUPPORTED) begin
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localparam numlines = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS;
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localparam numways = P.DCACHE_NUMWAYS;
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localparam linelen = P.DCACHE_LINELENINBITS;
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localparam linebytelen = linelen/8;
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localparam sramlen = P.CACHE_SRAMLEN;
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localparam cachesramwords = linelen/sramlen;
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localparam numwords = sramlen/P.XLEN;
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localparam lognumlines = $clog2(numlines);
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localparam loglinebytelen = $clog2(linebytelen);
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localparam lognumways = $clog2(numways);
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localparam tagstart = lognumlines + loglinebytelen;
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genvar index, way, cacheWord;
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logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [sramlen-1:0] cacheline;
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logic [P.XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [P.PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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for(index = 0; index < numlines; index++) begin
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for(way = 0; way < numways; way++) begin
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for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
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copyShadow #(.P(P), .tagstart(tagstart),
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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copyShadow(.clk,
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.start,
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.ram.RAM[index][P.PA_BITS-1-tagstart:0]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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// these dirty bit selections would be needed if dirty is moved inside the tag array.
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][P.PA_BITS+tagstart]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.ram.RAM[index]),
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.index(index),
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.cacheWord(cacheWord),
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.CacheData(CacheData[way][index][cacheWord]),
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.CacheAdr(CacheAdr[way][index][cacheWord]),
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.CacheTag(CacheTag[way][index][cacheWord]),
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.CacheValid(CacheValid[way][index][cacheWord]),
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.CacheDirty(CacheDirty[way][index][cacheWord]));
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end
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end
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end
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integer i, j, k, l;
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always @(posedge clk) begin
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if (startD) begin
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for(i = 0; i < numlines; i++) begin
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for(j = 0; j < numways; j++) begin
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for(l = 0; l < cachesramwords; l++) begin
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if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
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for(k = 0; k < numwords; k++) begin
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//cacheline = CacheData[j][i][0];
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// does not work with modelsim
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// # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
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// see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
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//ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
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/* verilator lint_off WIDTHTRUNC */
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// avoid lint error: address trunc warning for shadowram index
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ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
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/* verilator lint_on WIDTHTRUNC */
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end
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end
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end
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end
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end
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end
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end
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end
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flop #(1) doneReg1(.clk, .d(start), .q(startD));
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flop #(1) doneReg2(.clk, .d(startD), .q(done));
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endmodule
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module copyShadow import cvw::*; #(parameter cvw_t P,
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parameter tagstart, loglinebytelen, sramlen)
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(input logic clk,
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input logic start,
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input logic [P.PA_BITS-1:tagstart] tag,
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input logic valid, dirty,
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input logic [sramlen-1:0] data,
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input logic [32-1:0] index,
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input logic [32-1:0] cacheWord,
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output logic [sramlen-1:0] CacheData,
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output logic [P.PA_BITS-1:0] CacheAdr,
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output logic [P.XLEN-1:0] CacheTag,
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output logic CacheValid,
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output logic CacheDirty);
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logic [P.XLEN+1:0] TagExtend;
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logic [P.XLEN+1:0] IndexExtend;
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logic [P.XLEN+1:0] CacheWordExtend;
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logic [P.XLEN+1:0] CacheAdrExtend;
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assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)+2}{1'b0}}, tag};
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assign IndexExtend = {{{P.XLEN-32+2}{1'b0}}, index};
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assign CacheWordExtend = {{{P.XLEN-32+2}{1'b0}}, cacheWord};
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always_ff @(posedge clk) begin
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if(start) begin
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CacheTag = TagExtend[P.XLEN-1:0];
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CacheValid = valid;
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CacheDirty = dirty;
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CacheData = data;
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CacheAdrExtend = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8));
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end
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end
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assign CacheAdr = CacheAdrExtend[P.PA_BITS-1:0];
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endmodule
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