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84 lines
4.0 KiB
Systemverilog
84 lines
4.0 KiB
Systemverilog
///////////////////////////////////////////
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// hazard.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Determine forwarding, stalls and flushes
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module hazard(
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input logic clk,
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input logic reset,
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// Detect hazards
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input logic BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
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input logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
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input logic LSUStall, ICacheStallF,
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input logic FPUStallD, FStallD,
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input logic DivBusyE,FDivBusyE,
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// Stall & flush outputs
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output logic StallF, StallD, StallE, StallM, StallW,
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output logic FlushF, FlushD, FlushE, FlushM, FlushW
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);
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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// stalls and flushes
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// loads: stall for one cycle if the subsequent instruction depends on the load
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// branches and jumps: flush the next two instructions if the branch is taken in EXE
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// CSR Writes: stall all instructions after the CSR until it completes, except that PC must change when branch is resolved
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// this also applies to other privileged instructions such as M/S/URET, ECALL/EBREAK
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// Exceptions: flush entire pipeline
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// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
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// General stall and flush rules:
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// A stage must stall if the next stage is stalled
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// If any stages are stalled, the first stage that isn't stalled must flush.
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assign StallFCause = CSRWritePendingDEM && ~(TrapM | RetM | BPPredWrongE);
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assign StallDCause = (LoadStallD | StoreStallD | MulDivStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallECause = DivBusyE | FDivBusyE;
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assign StallMCause = 0;
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assign StallWCause = LSUStall | ICacheStallF;
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assign StallF = StallFCause | StallD;
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assign StallD = StallDCause | StallE;
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assign StallE = StallECause | StallM;
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assign StallM = StallMCause | StallW;
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assign StallW = StallWCause;
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//assign FirstUnstalledD = (~StallD & StallF & ~MulDivStallD);
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//assign FirstUnstalledE = (~StallE & StallD & ~MulDivStallD);
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assign FirstUnstalledD = (~StallD && StallF);
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assign FirstUnstalledE = (~StallE && StallD);
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assign FirstUnstalledM = (~StallM && StallE);
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assign FirstUnstalledW = (~StallW && StallM);
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// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
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assign FlushF = BPPredWrongE;
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assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
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assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE;
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assign FlushM = FirstUnstalledM | TrapM | RetM;
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assign FlushW = FirstUnstalledW | TrapM;
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endmodule
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