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https://github.com/openhwgroup/cvw
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57 lines
2.5 KiB
Systemverilog
57 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// tlbram.sv
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//
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// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Stores page table entries of cached address translations.
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// Outputs the physical page number and access bits of the current
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// virtual address on a TLB hit.
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module tlbram import cvw::*; #(parameter cvw_t P,
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parameter TLB_ENTRIES = 8) (
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input logic clk, reset,
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input logic [P.XLEN-1:0] PTE,
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input logic [TLB_ENTRIES-1:0] Matches, WriteEnables,
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output logic [P.PPN_BITS-1:0] PPN,
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output logic [11:0] PTEAccessBits,
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output logic [TLB_ENTRIES-1:0] PTE_Gs,
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output logic [TLB_ENTRIES-1:0] PTE_NAPOTs // entry is in NAPOT mode (N bit set and PPN[3:0] = 1000)
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);
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logic [P.XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; // stores the page table entries
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logic [P.XLEN-1:0] PageTableEntry;
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// RAM implemented with array of flops and AND/OR read logic
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tlbramline #(P) tlbramline[TLB_ENTRIES-1:0]
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(.clk, .reset, .re(Matches), .we(WriteEnables),
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.d(PTE), .q(RamRead), .PTE_G(PTE_Gs), .PTE_NAPOT(PTE_NAPOTs));
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or_rows #(TLB_ENTRIES, P.XLEN) PTEOr(RamRead, PageTableEntry);
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// Rename the bits read from the TLB RAM
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assign PTEAccessBits = {PageTableEntry[P.XLEN-1:P.XLEN-4] & {4{P.XLEN == 64}}, PageTableEntry[7:0]}; // for RV64 include N and PBMT bits and OR of reserved bits
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assign PPN = PageTableEntry[P.PPN_BITS+9:10];
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endmodule
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