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https://github.com/openhwgroup/cvw
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47 lines
2.8 KiB
Markdown
47 lines
2.8 KiB
Markdown
# CORE-V Wally Design Verification Test Plan
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CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction.
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| Tests | Section | TRL3 | TRL5 | Coverage Method | Status | Command |
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| ------------------- | -------------- | ------------ | ------ | --------------------- | ------ | ------- |
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| Verilator Lint | 5.3 | All configs | rv64gc | lint-wally | PASS | regression-wally --nightly |
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| Instructions | 3.7 | All configs | rv64gc | riscv-arch-test | PASS | regression-wally --nightly |
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| Privileged | 3.7 | All configs | rv64gc | wally-riscv-arch-test | PASS | regression-wally --nightly |
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| Floating-point | 5.11.7, 16.5.3 | rv{32/64}gc + derived | rv64gc | TestFloat | FAIL | regression-wally --nightly |
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| CoreMark | 21.1 | Many configs | rv64gc | CoreMark | | regression-wally --nightly |
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| Embench | 21.2 | rv32* | n/a | Embench | | regression-wally --nightly |
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| Cache PV | 21.3.1 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
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| Cache PV | 21.3.2 | rv{32/64}gc | rv64gc | TBD | TBD | TBD |
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| Linux Boot | 22.3.2 | rv64gc | rv64gc | TBD | TBD | TBD |
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| FPGA Linux Boot | 23.2 | | rv64gc | TBD | TBD | TBD |
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| Code Coverage | 5.11.10 | | rv64gc | TBD | TBD | TBD |
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| Functional Coverage | 5.11.11 | | rv64gc | TBD | TBD | TBD |
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* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
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* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
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* ***pending: Run random tests generated by risc-dv
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* Run CoreMark and Embench benchmarks.
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* Run performance validation against reference models for the branch predictor and caches.
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* Run the TestFloat suite against all precisions of all operations for the FPU unit.
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* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
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* Boot Buildroot Linux in lock-step against ImperasDV.
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* Boot Buildroot Linux on an FPGA and run programs.
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# Running Tests
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#
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# Detailed Test Plans
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The test plans for specific units are lined below:
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* Privileged Unit
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* Memory Management Unit
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* Peripherals
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* Branch Predictor Performance Validation
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* Cache Performance Validation
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Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. |