Ross Thompson b6ae6fea27 Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu ... only at the start of a request. Pending interrupt was used to start one of these suppressions; however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an interrupt becam pending then the the next request (eviction) made by the cache was also suppressed. This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request to the bus fsm, but the pending interrupt ignored the request. The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt it is better to use interrupt which will be disabled if the dcache is currently processing the evict.		2022-01-07 17:55:34 -06:00
..
slack-notifier	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wave-dos	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
buildrootBugFinder.py	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
fpga-wave.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
lint-wally	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
linux-wave.do	Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu	2022-01-07 17:55:34 -06:00
make-tests.sh	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
Makefile	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-06 23:04:33 +00:00
regression-wally.py	Removed imperas mmu tests; using wallypriv instead	2022-01-04 23:14:53 +00:00
sim-buildroot	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-buildroot-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-coremark-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-fp64	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-fp64-batch	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
sim-wally	some FPU test fixes	2022-01-06 23:03:20 +00:00
sim-wally-batch	some FPU test fixes	2022-01-06 23:03:20 +00:00
wally-buildroot-batch.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-buildroot.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-coremark.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-fp64-batch.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-fp64.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-pipelined-batch.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-pipelined-fpga.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wally-pipelined.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wave-all.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wave-coremark.do	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00
wave.do	Changes to wave file.	2022-01-05 14:16:59 -06:00