Ross Thompson 9adcf86a40 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. ... This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.		2021-12-19 14:57:42 -06:00
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cachereplacementpolicy.sv	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
cacheway.sv	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
dcache_ptw_interaction_README.txt	Fixed some typos in the dcache ptw interaction documentation.	2021-12-13 15:47:20 -06:00
dcache.sv	minro change. comments about needed changes in dcache.	2021-12-19 13:53:02 -06:00
dcachefsm.sv	minro change. comments about needed changes in dcache.	2021-12-19 13:53:02 -06:00
icache.sv	Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.	2021-12-19 14:57:42 -06:00
icachefsm.sv	Possible fix for icache deadlock interaction with hptw.	2021-12-17 14:38:25 -06:00
sram1rw.sv	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00