David Harris 72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.		2021-09-15 13:14:00 -04:00
..
cache	Fixed dcache to prevent latches in FPGA synthesized design.	2021-09-11 12:03:48 -05:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
generic	Fixed bug with or_rows.	2021-09-11 15:51:11 -05:00
hazard	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
ieu	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
ifu	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
lsu	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
mmu	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
muldiv	Restored old integer divider	2021-09-12 22:07:52 -04:00
privileged	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
uncore	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
wally	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00