cvw/wally-pipelined/src
2021-07-05 20:35:31 -04:00
..
cache Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:55:24 -04:00
ebu Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
fpu Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
generic Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
hazard Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
ieu Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
ifu Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
lsu Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00
mmu Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
muldiv Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
privileged Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
uncore Simplified PLIC with generate 2021-07-04 19:17:15 -04:00
wally Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00