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https://github.com/openhwgroup/cvw
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58 lines
2.5 KiB
Systemverilog
58 lines
2.5 KiB
Systemverilog
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///////////////////////////////////////////
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// zbb.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
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// Created: 2 February 2023
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// Modified: March 6 2023
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//
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// Purpose: RISC-V ZBB top level unit
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module zbb #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, RevA, B, // Operands
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input logic W64, // Indicates word operation
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input logic LT, // lt flag
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input logic LTU, // ltu flag
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input logic BUnsigned, // max/min (signed) flag
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input logic [2:0] ZBBSelect, // ZBB Result select signal
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output logic [WIDTH-1:0] ZBBResult); // ZBB result
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logic lt; // lt given signed/unsigned
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logic [WIDTH-1:0] CntResult; // count result
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logic [WIDTH-1:0] MinMaxResult; // min, max result
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logic [WIDTH-1:0] ByteResult; // byte results
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logic [WIDTH-1:0] ExtResult; // sign/zero extend results
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mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
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cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
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byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
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ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
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// ZBBSelect[2] differentiates between min(u) vs max(u) instruction
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mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);
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// ZBB Result select mux
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mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult);
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endmodule
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