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https://github.com/openhwgroup/cvw
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181 lines
11 KiB
Systemverilog
181 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// bmuctrl.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 16 February 2023
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// Modified: 6 March 2023
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//
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// Purpose: Top level bit manipulation instruction decoder
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module bmuctrl import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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// Decode stage control signals
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input logic StallD, FlushD, // Stall, flush Decode stage
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input logic [31:0] InstrD, // Instruction in Decode stage
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input logic ALUOpD, // Regular ALU Operation
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output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
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output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
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output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage
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output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
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output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage
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output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage
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output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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output logic [2:0] ALUSelectD, // ALU select
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output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
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output logic [2:0] ZBBSelectE, // ZBB mux select signal
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output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
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output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
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output logic BMUActiveE // Bit manipulation instruction being executed
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);
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logic [6:0] OpD; // Opcode in Decode stage
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logic [2:0] Funct3D; // Funct3 field in Decode stage
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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logic RotateD; // Indicates if rotate instruction in Decode Stage
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logic MaskD; // Indicates if zbs instruction in Decode Stage
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logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
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logic [2:0] BALUControlD; // ALU Control signals for B instructions
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logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations
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logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage
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`define BMUCTRLW 17
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logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
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// Extract fields
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assign OpD = InstrD[6:0];
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assign Funct3D = InstrD[14:12];
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assign Funct7D = InstrD[31:25];
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assign Rs2D = InstrD[24:20];
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// Main Instruction Decoder
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always_comb begin
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// BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD
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BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction;
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if (P.ZBA_SUPPORTED) begin
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
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endcase
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if (P.XLEN==64)
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casez({OpD, Funct7D, Funct3D})
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
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endcase
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end
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if (P.ZBB_SUPPORTED) begin
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
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17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
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BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
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else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
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// // coverage off: This case can't occur in RV64
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// 17'b0110011_0000100_100: if (P.XLEN == 32)
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// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
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// // coverage on
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
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17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
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17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
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BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu
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endcase
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if (P.XLEN==32)
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32)
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endcase
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else if (P.XLEN==64)
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casez({OpD, Funct7D, Funct3D})
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17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
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17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
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17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
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17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
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BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
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endcase
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end
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if (P.ZBC_SUPPORTED)
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
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endcase
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if (P.ZBS_SUPPORTED) begin // ZBS
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
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endcase
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if (P.XLEN==32) // ZBS 64-bit
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
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endcase
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else if (P.XLEN==64) // ZBS 64-bit
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casez({OpD, Funct7D, Funct3D})
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17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
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17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
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17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
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17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
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endcase
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end
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if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
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casez({OpD, Funct7D, Funct3D})
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17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
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17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
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17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
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17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
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endcase
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end
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// Unpack Control Signals
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assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD;
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// Pack BALUControl Signals
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assign BALUControlD = {RotateD, MaskD, PreShiftD};
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// Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition
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assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
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// BMU Execute stage pipieline control register
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flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
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endmodule
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