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57 lines
2.5 KiB
Systemverilog
57 lines
2.5 KiB
Systemverilog
///////////////////////////////////////////
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// tlbram.sv
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//
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// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Stores page table entries of cached address translations.
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// Outputs the physical page number and access bits of the current
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// virtual address on a TLB hit.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module tlbram #(parameter TLB_ENTRIES = 8) (
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input logic clk, reset,
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input logic [`XLEN-1:0] PTE,
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input logic [TLB_ENTRIES-1:0] Matches, WriteEnables,
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output logic [`PPN_BITS-1:0] PPN,
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output logic [7:0] PTEAccessBits,
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output logic [TLB_ENTRIES-1:0] PTE_Gs
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);
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logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
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logic [`PPN_BITS+9:0] PageTableEntry;
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// RAM implemented with array of flops and AND/OR read logic
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tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0]
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(.clk, .reset, .re(Matches), .we(WriteEnables),
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.d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs));
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or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry);
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// Rename the bits read from the TLB RAM
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assign PTEAccessBits = PageTableEntry[7:0];
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assign PPN = PageTableEntry[`PPN_BITS+9:10];
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endmodule
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