Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-24 05:24:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
84256924e7
cvw/synthDC
History
Madeleine Masser-Frye 84256924e7 cleanup, plots for paper
2022-06-15 18:28:36 +00:00
..
scripts added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
.synopsys_dc.setup added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
bestSynths.csv cleanup, plots for paper 2022-06-15 18:28:36 +00:00
extractSummary.py updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Makefile automate synth 2022-04-25 16:03:32 +00:00
oldBestSynths.csv fresh set of syntheses 2022-06-15 18:26:16 +00:00
oldPpaData.csv fresh set of syntheses 2022-06-15 18:26:16 +00:00
ppa filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
ppaAnalyze.py cleanup, plots for paper 2022-06-15 18:28:36 +00:00
ppaData.csv fresh set of syntheses 2022-06-15 18:26:16 +00:00
ppaEquations.csv equation table, plot adjustments 2022-06-10 21:11:39 +00:00
ppaFitting.csv restored functionality of makeCoefTable() 2022-06-09 00:07:51 +00:00
ppaSynth.py fixed importing of area-optimized synths, overlayed them on PPA plots, accounted for mux outliers, fixed flop adjustments 2022-06-07 18:31:49 +00:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
runConfigsSynth.sh Ignore intermediate files in synthesis sweeps 2022-04-27 13:12:04 +00:00
runFrequencySynth.sh Ignore intermediate files in synthesis sweeps 2022-04-27 13:12:04 +00:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.