Rose Thompson 588e1caeba Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.		2024-01-06 22:29:16 -06:00
..
ahbcacheinterface.sv	Added partial code for uncached amo operations.	2023-12-29 15:07:20 -06:00
ahbinterface.sv	Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries.	2024-01-06 22:29:16 -06:00
buscachefsm.sv	Added partial code for uncached amo operations.	2023-12-29 15:07:20 -06:00
busfsm.sv	More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.	2023-05-24 14:56:02 -05:00
controllerinput.sv	Update controllerinput.sv	2023-06-10 18:26:06 -07:00
ebu.sv	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
ebufsmarb.sv	Fixed warnings of signed conversion and for Design Compiler	2023-10-24 14:01:43 -07:00