mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
31 lines
1.1 KiB
Markdown
31 lines
1.1 KiB
Markdown
# core-v-wally Design Verification Test Plan
|
|
|
|
This document outlines the test plan for the Wally rv64gc configuration to reach Technology Readiness Level 5.
|
|
|
|
1. Pass riscv-arch-test
|
|
2. Boot Linux
|
|
3. FPU pass all TestFloat vectors
|
|
4. Performance verification: Caches and branch predictor miss rates match independent simulation
|
|
5. Directed tests
|
|
- Privileged unit: Chapter 5 test plan
|
|
- MMU: PMA, PMP, virtual memory: Chapter 8 test plan
|
|
- Peripherals: Chapter 16 test plan
|
|
6. Random tests
|
|
- riscdv tests
|
|
7. Coverage tests
|
|
- Directed tests to bring coverage up to 100%.
|
|
- Statement, experssion, branch, condition, FSM coverage in Questa
|
|
- Do not measure toggle coverage
|
|
|
|
All tests operate correctly in lock-step with ImperasDV
|
|
|
|
Open questions:
|
|
1. How to define extent of riscdv random tests needed?
|
|
2. What other directed tests?
|
|
PMP Tests
|
|
Virtual Memory Tests
|
|
How to define pipeline tests?
|
|
Simple ones like use after load stall are not important.
|
|
Hard ones such as page table walker fault during data access while I$ access is pending are hard to articulate and code
|
|
Is there an example of a good directed pipeline test plan & implementation
|